In the next section of the chapter, we define logic implementation by using 2M1M cells and describe variety of in-memory digital logic 2M1M gates. In the second section of the chapter, we discuss a 2M1M memristor switch and its functionality which can be applied into memory crossbars and enables both memory and logic functions. These composite cells can be designed to be adapted into different design needs can enhance the performance of the memristor crossbar array while preserving their advantages in terms of area and/or energy efficiency. along with their drawbacks and implementation limitations. In the first section of this chapter, we briefly discuss compute-in-memory memristive architectural concepts and specifically investigate the current state off the art composite memristor-based switch cells. In this chapter, we discuss the compute-in-memory memristive architectures and develop a 2M1M crossbar array which can be applied for both memory and logic applications. The simulation results show that the proposed memory cell has superior performance compared with current NAND/NOR flash memories and other memristor-based cells found in the technical literature. It is shown that due to the low voltage across the memristor during a READ operation, a refresh operation is required when multiple consecutive READ operations occur. Particular emphasis is devoted to the threshold characterization of the memristance with respect to its ON/OFF states. Simulation results are given to assess its performance in terms of WRITE/READ times, transistor scaling, and power dissipation. A detailed treatment of the two basic operations (WRITE and READ) of the memory circuit with respect to the memristor is provided. Macroscopic models are utilized to characterize the nonvolatile feature of the memory cell (for example, an ambipolar transistor is modeled by a circuit consisting of two transmission gates and two CMOS transistors). This paper presents a novel circuit of a memory cell consisting of a memristor and ambipolar transistors.
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